Electronic circuits are increasingly being optimized for lower power and smaller size requirements for better incorporation into integrated circuit designs. The increase in complexity and gate count within integrated circuits also requires that electrical circuit testability be addressed in the designs of integrated circuits. One general methodology of integrated circuit testability is referred to as Level Sensitive Scan Design (LSSD). A LSSD circuit complies with a set of design rules that enhances the observability and controllability of digital circuit elements so as to enhance testability of a complex digital design circuit.
In a LSSD design, scan chains provide access and testing for the internal circuits of large-scale integrated (LSI) circuits, very large scale integrated (VLSI) circuits, and other integrated circuits. The scan chains can be configured as one long chain or multiple short chains. FIG. 1 illustrates a block diagram of an exemplary LSSD design circuit 100 The exemplary LSSD design circuit 100 includes multiple scan chains 110 interfacing with the logic circuitry 120.
FIG. 2 is a block diagram of a scan chain 110. The scan chain 110 generally includes a set of shift register latch blocks or data storage elements 210 connected in a series configuration.
These latch blocks 210 incorporate a design that allows data to be loaded into a shift register through an alternate data input. This alternate input is generally used for circuit test and stimulation and is sometimes referred to as a “scan input” since it allows a pre-defined state to be “scanned” into the sequential circuit using these register latch blocks. Loading a latch block with a particular value allows, for example, placing a sequential logic circuit into a desired state.
FIG. 3 is a block diagram of a typical latch block 210. The latch block 210 or shift register latch includes a pair of latches L1 and L2 where L1 310 is the “master” latch and L2 318 is the “slave” latch. The L1 latch or master latch 310 has two data ports, a system input port SYS 302 and an alternate data input port SCAN 306 and may be updated by either a functional clock C1 304 or a scan clock A 308.
In normal operation of the shift register block 210, data is provided on the system input port SYS 302 and this data value is selected for storage into latch L1 310 upon a transition of the functional clock C1 304 from low to high. The shift register block 210 is also able to select for storage data from the alternate data input port SCAN 306 by providing a data value on the alternate data input port SCAN 306 and then causing this value to be stored into latch L1 310 upon a transition of the scan clock “a” 308. Once a data value is stored in L1 310, this value is available, after a propagation delay, at the L1 Output 312. The logical value that is present on the L1 Output 312 is stored into latch L2 318 upon a transition of shift clock “b” 314 (or shift clock c2) from a logical low level to a logical high level. After the L1 Output 312 is stored into the L2 latch or slave latch 318 that logic value is available, after a propagation delay, on the L2 output 320.
A scan chain provides access to the internal parts of a chip and its function is critical in testing a chip. A problem arises, however, when a scan chain fails. Often scan chain fallout occurs early in the life cycle for new chip technology development, and quickly diagnosing any scan fails is critical to improving the process so that targeted manufacturing yield levels can be achieved.
Generally, scan chain fails can be divided into two categories: DC defects and broken. A broken scan chain is one that will not operate under any conditions (e.g., voltage, frequency, temperature). A scan chain containing DC defects will only operate under certain conditions (e.g., only between 1.2V and 1.3V). The condition or conditions under which a scan chain operates or fails will be referred to as the “operating region” and “failing region”, respectively.
One method provides some success in diagnosing and locating a first failed register latch in a scan chain. This method contains the steps of loading the scan chain in the operating region, and unloading the scan chain in the failing region.
Another method provides some success in diagnosing and locating a last failed register latch in a scan chain. This method contains the steps of loading the scan chain in the failing region, and unloading the scan chain in the operating region.
To illustrate these methods, consider the following example of a scan chain 400 consisting of eight latches as shown in FIG. 4. Assume there is a defect 450 at the output of RML5 408 that causes the chain to be stuck-at “1” in the failing region, where RML means “Register Measure Latch.” Using the first method, the scan chain 400 is loaded with all zeroes (0's) in the operating region, resulting in the value of each latch to be a zero or RML(1:8)=‘00000000’. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 400 from scan input 202 is shown in block 420. Next, the scan chain 400 is switched into the failing region and unloaded. The following data is attained: RML(1:8)=‘00001111’. From this data, it may be diagnosed that the DC fail occurs on RML5 408. The output taken from scan output 204 is shown in block 422 after all of the input value of zero has propagated through the scan chain 400.
To illustrate the second prior art method shown in FIG. 5 is a block diagram of an exemplary scan chain circuit with a DC defect 450 again at the output of RML 5 being scanned. Using the second method, the scan chain 400 is loaded with all zeroes (0's) in the failing region, resulting in RML(1:8)=‘11110000’. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 400 from scan input 202 is shown in block 520. Next, the scan chain is switched into the operating region and unloaded. The following data is attained: RML(1:8)=“11110000”. The output taken from scan output 204 is shown in block 522 after all of the input value of zero has propagated through the scan chain 400. From this data, it may be diagnosed that the DC fail occurs on RML5 408.
Now consider the following example of a scan chain 600 consisting of eight latches with two DC defects 652 and 654 as shown in FIG. 6. Assume there are defects at the outputs of RML5 608 and RML3 612 that cause the chain to be stuck-at “1” in the failing region. Using the first method, the scan chain 600 is loaded with all zeroes (0's) in the operating region, resulting in the value of each latch to be a zero or RML(1:8)=‘00000000’. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 600 from scan input 602 is shown in block 620. Next, the scan chain 600 is switched into the failing region and unloaded. The following data is attained: RML(1:8)=‘00111111’. The output taken from scan output 604 is shown in block 622 after all of the input value of zero has propagated through the scan chain 600. From this data, it may be diagnosed that the DC fail occurs on RML3 412.
To illustrate the second prior art method shown in FIG. 7 is a block diagram of an exemplary scan chain circuit with a two DC defect 652 and 654 being scanned. Using the second method, the scan chain is loaded with all zeroes (0's) in the failing region, which results in RML(1:8)=‘1111000’. The propagation during each of the clock cycles (i.e. cycles 1–8) across the scan chain 600 from scan input 602 is shown in block 720. Next, the scan chain is switched into the operating region and unloaded. The following data is attained: RML(1:8)=‘1111000’. The output taken from scan output 604 is shown in block 722 after all of the input value of zero has propagated through the scan chain 600. From this data, it may be diagnosed that the DC fail or fault occurs on RML5 408.
When there are multiple DC defects in a scan chain, only the first and last defect in the scan chain can be diagnosed and identified using the two mentioned methods. Although this is useful, if there are multiple defects, for example a third defect at RML 3 which is between defect 652 of RML4 and defect 654 This third defect or inner defect (inner meaning after the first and last defect of a chain) is to be detected by these prior art methods, either separately or combined. Further any multiple defects that occur between a first defect and a last defect are not detected by these prior art method either, again either separately or combined.
Accordingly, there is a need for a method to diagnose and locate all multiple DC defects in a scan chain.